System And Method For Processor Power Delivery And Thermal Management

ABSTRACT

A power interconnection system comprising a plurality of z-axis compliant connectors passing power and ground signals between a first circuit board to a second circuit board is disclosed. The interconnection system provides for an extremely low impedance through a broad range of frequencies and allows for large amounts of current to pass from one substrate to the next either statically or dynamically. The interconnection system may be located close to the die or may be further away depending upon the system requirements. The interconnection may also be used to take up mechanical tolerances between the two substrates while providing a low impedance interconnect.

REFERENCE TO RELATED APPLICATIONS

The Present application is a Continuation Application of U.S. patentapplication Ser. No. 11/749,070, entitled “System And Method ForProcessor Power Delivery And Thermal Management, filed 15 May 2007.

The '070 application is a Continuation Application of U.S. patentapplication Ser. No. 10/401,103, entitled “Method For Supplying A Z-AxisUltra Low Power Impedance Interconnection Between A DC-To-DC ConverterAnd A Processor,” filed 25 Mar. 2003, now abandoned.

The '103 application is a Continuation Application of U.S. patentapplication Ser. No. 10/036,957, entitled “Ultra-Low Impedance PowerInterconnector System For Electronic Packages,” filed 20 Dec. 2001.

The '957 application is a Continuation-In-Part Application of U.S.patent application Ser. No. 09/432,878, entitled “Inter-CircuitEncapsulated Packaging For Power Delivery,” filed 2 Nov. 1999, now U.S.Pat. No. 6,356,448.

The '957 Application is also a Continuation-In-Part Application of U.S.patent application Ser. No. 09/785,892, entitled “Apparatus ForProviding Power To A Microprocessor With Integrated Thermal And EMIManagement,” filed 16 Feb. 2001, now U.S. Pat. No. 6,452,113.

The '957 Application is also a Continuation-In-Part Application of U.S.patent application Ser. No. 09/885,780, entitled “Inter-CircuitEncapsulated Packaging,” filed 19 Jun. 2001, now abandoned. The '780application is a Continuation Application of U.S. patent applicationSer. No. 09/353,428, entitled “Inter-Circuit Encapsulated Packaging,”filed 15 Jul. 1999, now U.S. Pat. No. 6,304,450.

The '957 Application is also a Continuation-In-Part of U.S. patentapplication Ser. No. 09/727,016, entitled “EMI Containment UsingInter-Circuit Encapsulated Packaging Technology,” filed 28 Nov. 2000,now abandoned.

The '016 Application claims the benefit of the following U.S.Provisional Patent Applications:

U.S. Provisional Patent Application No. 60/167,792, entitled “EMIContainment Using Inter-Circuit Encapsulated Packaging Technology,”filed 29 Nov. 1999;

U.S. Provisional Patent Application No. 60/171,065, entitled“Inter-Circuit Encapsulated Packaging Technology,” filed 16 Dec. 1999;

U.S. Provisional Patent Application No. 60/183,474, entitled “DirectAttach Power/Thermal With Incep Technology,” filed 18 Feb. 2000;

U.S. Provisional Patent Application No. 60/187,777, entitled “NextGeneration Packaging For EMI Containment, Power Delivery, And ThermalDissipation Using Inter-Circuit Encapsulated Packaging Technology,”filed 8 Mar. 2000;

U.S. Provisional Patent Application No. 60/196,059, entitled “EMI FrameWith Power Feed-Throughs And Thermal Interface Material In An AggregateDiamond Mixture,” filed 10 Apr. 2000;

U.S. Provisional Patent Application No. 60/219,813, entitled“High-Current Microprocessor Power Delivery Systems,” filed 21 Jul.2000; and

U.S. Provisional Patent Application No. 60/232,971, entitled “IntegratedPower Distribution And Semiconductor Package,” filed 14 Sep. 2000.

The '957 Application is also a Continuation-In-Part Application of U.S.patent application Ser. No. 09/798,541, entitled “Thermal/MechanicalSpringbeam Mechanism For Heat Transfer From Heat Source To HeatDissipating Device,” filed 2 Mar. 2001, now abandoned.

The '541 Application claims the benefit of U.S. Provisional PatentApplication No. 60/186,769, entitled “Thermacep Spring Beam,” filed 3Mar. 2000.

The '957 Application is also a Continuation-In-Part Application of U.S.patent application Ser. No. 09/910,524, entitled “High PerformanceThermal/Mechanical Interface For Fixed Gap References For High Heat FluxAnd Power Semiconductor Applications,” filed 30 Jul. 2001, nowabandoned.

The '524 Application claims the benefit of U.S. Provisional PatentApplication No. 60/219,506, entitled “High PerformanceThermal/Mechanical Interface,” filed 20 Jul. 2000.

The '957 Application is also a Continuation-In-Part Application of U.S.patent application Ser. No. 09/921,153, entitled “Vapor Chamber WithIntegrated Pin Array,” filed 2 Aug. 2001, now U.S. Pat. No. 6,490,160.

The '153 Application ('160 Patent) claims the benefit of the followingU.S. Provisional Patent Applications:

U.S. Provisional Patent Application No. 60/222,386, entitled “HighDensity Cicrular “PIN” Connector For High Speed Signal Interconnect,”filed 2 Aug. 2000; and

U.S. Provisional Patent Application No. 60/222,407, entitled “VaporHeatsink Combination For High Efficiency Thermal Management,” filed 2Aug. 2000.

All the above-identified Patent Applications (and, where applicable,Patents) are hereby incorporated by reference herein in theirentireties. Additionally, the following Patent Applications (and, whereapplicable, Patents) are also hereby incorporated herein by reference intheir entireties:

U.S. patent application Ser. No. 09/353,428, entitled “Inter-CircuitEncapsulated Packaging,” filed 15 Jul. 1999, now U.S. Pat. No.6,304,450;

U.S. patent application Ser. No. 09/432,878, entitled “Inter-CircuitEncapsulated Packaging For Power Delivery,” filed 2 Nov. 1999, now U.S.Pat. No. 6,356,448;

U.S. patent application Ser. No. 09/785,892, entitled “Apparatus ForProviding Power To A Microprocessor With Integrated Thermal And EMIManagement,” filed 16 Feb. 2001, now U.S. Pat. No. 6,452,113;

U.S. Provisional Patent Application No. 60/1,67,792, entitled “EMIContainment Using Inter-Circuit Encapsulated Packaging Technology,”filed 29 Nov. 1999;

U.S. Provisional Patent Application No. 60/171,065, entitled“Inter-Circuit Encapsulated Packaging Technology,” filed 16 Dec. 1999;

U.S. Provisional Patent Application No. 60/183,474, entitled “DirectAttach Power/Thermal With Incep Technology,” filed 18 Feb. 2000;

U.S. Provisional Patent Application No. 60/186,769, entitled “ThermacapSpring Beam,” filed 3 Mar. 2000;

U.S. Provisional Patent Application No. 60/187,777, entitled “NextGeneration Packaging For EMI Containment, Power Delivery, And ThermalDissipation Using Inter-Circuit Encapsulated Packaging Technology,”filed 8 Mar. 2000;

U.S. Provisional Patent Application No. 60/196,059, entitled “EMI FrameWith Power Feed-Throughs And Thermal Interface Material In An AggregateDiamond Mixture,” filed 10 Apr. 2000;

U.S. Provisional Patent Application No. 60/219,506, entitled “HighPerformance Thermal/Mechanical Interface,” filed 20 Jul. 2000;

U.S. Provisional Patent Application No. 60/219,813, entitled“High-Current Microprocessor Power Delivery Systems,” filed 21 Jul.2000;

U.S. Provisional Patent Application No. 60/222,386, entitled “HighDensity Circular “PIN” Connector For High Speed Signal Interconnect,”filed 2 Aug. 2000;

U.S. Provisional Patent Application No. 60/222,407, entitled “VaporHeatsink Combination For High Efficiency Thermal Management,” filed 2Aug. 2000; and

U.S. Provisional Patent Application No. 60/232,971, entitled “IntegratedPower Distribution And Semiconductor Package,” filed 14 Sep. 2000.

BACKGROUND OF THE PRESENT APPLICATION

The Present Application relates generally to systems and methods forinterconnecting electronic packages and in particular to a powerinterconnection system mating between substrates to enable a lowimpedance disconnectable power delivery path between the power sourceand the load of an electronic package.

High-speed microprocessor packaging must be designed to provideincreasingly small form-factors. Meeting end user performancerequirements with minimal form-factors while increasing reliability andmanufacturability presents significant challenges in the areas of powerdistribution, thermal management and electromagnetic interference (EMI)containment.

To increase reliability and reduce thermal dissipation requirements,newer generation processors are designed to operate with reduced voltageand higher current. Unfortunately, this creates a number of designproblems.

First, the lowered operating voltage of the processor places greaterdemands on the power regulating circuitry and the conductive pathsproviding power to the processor. Typically, processors require supplyvoltage regulation to within 10% of nominal. In order to account forimpedance variations in the path from the power supply to the processoritself, this places greater demands on the power regulating circuitry,which must then typically regulate power supply voltages to within 5% ofnominal.

Lower operating voltages have also lead engineers away from centralizedpower supply designs to distributed power supply architectures in whichpower is bused where required at high voltages and low current, where itis converted to the low-voltage, high-current power required by theprocessor from nearby power conditioning circuitry.

While it is possible to place power conditioning circuitry on theprocessor package itself, this design is difficult to implement becauseof the unmanageable physical size of the components in the powerconditioning circuitry (e.g. capacitors and inductors), and because theaddition of such components can have a deleterious effect on processorreliability. Such designs also place additional demands on the assemblyand testing of the processor packages as well.

Further exacerbating the problem are the transient currents that resultfrom varying demands on the processor itself. Processor computingdemands vary widely over time, and higher clock speeds and powerconservation techniques such as clock gating and sleep mode operationgive rise to transient currents in the power supply. Such powerfluctuations can require changes of thousands of amps within a fewmicroseconds. The resulting current surge between the processor and thepower regulation circuitry can create unacceptable spikes in the powersupply voltage

(e.g., dv=I*R+L*di/dt)

The package on which the device (die) typically resides must beconnected to other circuitry in order for it to communicate and getpower into and out of the device. Because the current slew-rates may bevery high, a low impedance interconnection system is often needed toreduce voltage excursions between the power source and load which, ifleft unchecked, may cause false switching due to the reduced voltageseen at the load from a large voltage drop across the interconnect.

The technology of vertically stacking electronic substrates has beenutilized for a number of years. As one example, U.S. Pat. No. 5,734,555,issued to McMahon (which is hereby incorporated by reference herein)discloses a method by which a circuit board containing power conversionelements is coplanar located over a circuit board containing anintegrated circuit. The interconnect between the power conversionsubstrate and the integrated circuit substrate utilizes pins which donot provide a low impedance power path to the integrated circuit.Further, the McMahon device cannot be easily disassembled because thepins are permanently connected to the substrates. As another example,U.S. Pat. No. 5,619,339, (which is hereby incorporated by referenceherein) issued to Mok discloses a printed circuit board (PCB) isvertically displaced over a multi-chip module (MCM) with electricalcommunication between the two substrates (the PCB and the MCM)established by a compliant interposer which contains “fuzz buttons”which communicate with pads located on each substrate. Although such anapproach does provide for disassembly of the two substrates, e.g., theMCM and the PCB, the approach does not provide for large ‘Z’ axiscompliance to accommodate manufacturing tolerances, and does not teachthe use of a contact design that is capable of handling large amounts ofDC current. Further, this design requires the use of a compliantinterposer. In order to handle such large amounts of current, the numberof contacts would have to be increased dramatically, which wouldincrease the inductance between the source and the load device.Furthermore, such a large array of such contacts would require a largeamount of force to be applied to maintain contact and will not result ina space-efficient design.

From the foregoing, it can be seen that there is a need for a lowimpedance power interconnect between the power dissipating device andthe power source. It can also be seen that this impedance must be low ininductance and resistance throughout a wide frequency band in order toensure that the voltage drops across the interconnect are mitigatedacross it during dynamic switching of power. It can also be seen thatthe interconnect should provide large ‘z’ axis compliance and permitseparation of the assembly without desoldering or similar measures.

SUMMARY OF THE PRESENT APPLICATION

To address the requirements described above, the Present Applicationdiscloses an apparatus for providing power to a power dissipatingdevice. The apparatus comprises a first circuit board and a secondcircuit board, and a plurality of compliant conductors disposed betweenfirst circuit board and the second circuit board.

The first circuit board includes a power conditioner circuit, and afirst side and a second side having a plurality of first circuit boardcontacts thereon. The first circuit board contacts include a first setof first circuit board contacts communicatively coupled to a first powerconditioner circuit connector and a second set of first circuit boardcontacts communicatively coupled to a second power conditioning circuitconnector.

The second circuit board includes the power dissipating device mountedthereto and a plurality of second circuit board contacts disposed on afirst side of the second circuit board facing the second side of thefirst circuit board. The second circuit board also includes a first setof second circuit board contacts communicatively coupled to a powerdissipating device first connector and a second set of second circuitboard contacts communicatively coupled to a second connector of thepower dissipating device.

The plurality of z-axis compliant conductors includes a first set ofz-axis compliant conductors disposed between the first set of firstcircuit board contacts and the first set of second circuit boardcontacts and a second set of z-axis compliant conductors disposedbetween the second set of first circuit board contacts and the secondset of second circuit board contacts.

The first set of first circuit board contacts, the first set of z-axiscompliant conductors, and the first set of second circuit board contactsdefine a plurality of first paths from the first circuit board to thesecond circuit board and wherein the second set of circuit boardcontacts, the second set of z-axis compliant conductors, and the secondset of second circuit board contacts define a plurality of second pathsfrom the first circuit board to the second circuit board.

The Present Application provides a spring-like structure whichdisconnectably connects between two or more substrates (such as aprinted circuit board or IC package) whereby the connection isdisconnectable at least on one of the two sides. The interconnectionsystem provides for an extremely low impedance through a broad range offrequencies and allows for large amounts of current to pass from onesubstrate to the next either statically or dynamically. Theinterconnection system may be located close to the die or may be furtheraway depending upon the system requirements. The interconnection mayalso be used to take up mechanical tolerances between the two substrateswhile providing a low impedance interconnect. Due to the low impedanceconnection, the design permits the displacement of bypass capacitors onthe circuit board having the power dissipating device, and placement ofthese capacitors on the circuit board having the power conditioningcircuitry, resulting in ease of manufacturing and improved reliabilityof the power dissipating device assembly.

The Present Application reduces or eliminates the need for supportingelectronic components for the power dissipating device on the substrate,since the interconnect impedance between the power source and theelectronic device is sufficiently low so that all or most of thesupporting electronics can be located on the substrate containing thepower source. Since the Present Application does not use any socketconnectors to supply power to the device, such socket connectors arefreed to provide additional signals.

BRIEF DESCRIPTION OF THE FIGURES

The organization and manner of the structure and operation of thePresent Application, together with further objects and advantagesthereof, may best be understood by reference to the following DetailedDescription, taken in connection with the accompanying Figures, whereinlike reference numerals identify like elements, and in which:

FIGS. 1A and 1B are diagrams showing exploded views of theinterconnection system as placed between two substrates, e.g., a voltageregulator module (VRM) mounted over a power dissipating device;

FIGS. 1C-1E are diagrams showing different electrical arrangements ofthe contacts;

FIGS. 2A-2C are diagrams showing exploded views of the interconnectionsystem as placed between a processor substrate and a motherboard, theinterconnection system occurring on the sides of the processorsubstrate;

FIG. 2D are diagrams depicting a view of section A-A of FIG. 2C;

FIGS. 3A-3C are diagrams showing a simple stackup cross-section of theinterconnection system as placed between two substrates;

FIGS. 4A and 4B are diagrams showing an embodiment of a cantilever beamthat may be used to implement the z-axis compliant contacts;

FIGS. 5A-5D are diagrams showing further embodiments of a cantileveredbeam in which the different features of the beam construction areutilized to reduce the connection inductance of the compliant contacts;

FIG. 6A is an isometric view of an assembly showing multiple pairs ofz-axis compliant conductors arranged in two rows within an insulatingframe structure;

FIG. 6B is an isometric view of a pair of spring contacts in a scissorconfiguration;

FIG. 6C is a section view showing how spring contacts arranged in ascissor configuration can be used to interconnect the first and secondcircuit boards;

FIG. 6D is a plan view of the substrate in the embodiments illustratedin FIGS. 6A-6C;

FIG. 6E is a diagram illustrating an another embodiment of the z-axiscompliant conductors and contact pads on the first circuit board;

FIG. 6F is a diagram illustrating another embodiment of the PresentApplication in which a continuous linear contact pads on the secondcircuit board are used without opposing scissor configurationz-compliant conductors;

FIG. 6G illustrates an embodiment of the Present Application wherein thez-axis compliant conductors are not permanently affixed to any contactson either the first circuit board or the second circuit board, thuspermitting easy disassembly;

FIG. 6H is a diagram presenting another embodiment of the PresentApplication in which an x-axis compliant conductor interfaces with edgecontacts on the second circuit board;

FIG. 6I is a diagram presenting another embodiment of the z-axiscompliant conductors having reduced impedance;

FIG. 6J is a diagram presenting a cross section of the embodimentillustrated in FIG. 6I;

FIG. 7 is a plan view illustrating another embodiment of the PresentApplication utilizing multiple rows of z-axis compliant conductors;

FIG. 8 is a diagram presenting a prior art stack up arrangement of amicroprocessor substrate;

FIG. 9 is a diagram presenting an improved power distribution systemmade possible by the Present Application;

FIG. 10 is a diagram illustrating an embodiment of the PresentApplication wherein the power conditioning unit is partitioned toprovide multiple power signals, each differing in phase, and each beingdistributed to different sides of the power dissipating device;

FIG. 11A is a diagram of a section view of direct power attachment to asubstrate;

FIG. 11B is a top view of FIG. 11A;

FIG. 11C is a diagram of a blow-up of a section of view A-A in FIG. 11A;

FIG. 12 is a diagram of a split-wedge washer;

FIG. 13 is a diagram that shows the attachment of a section of FIGS. 11Cand 12 combined;

FIG. 14 is a diagram of a high level assembly view;

FIG. 15 is a diagram of a low inductance frame standoff;

FIG. 16 is a diagram of an assembly view with low inductance standoffand interface board;

FIG. 17 is a diagram of a cross section view with low inductancestandoff and interface board; and

FIG. 18 is a diagram of an exploded view of FIG. 16.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

While the Present Application may be susceptible to embodiment indifferent forms, there is shown in the Figures, and will be describedherein in detail, specific embodiments, with the understanding that thedisclosure is to be considered an exemplification of the principles ofthe Present Application, and is not intended to limit the PresentApplication to that as illustrated.

In the illustrated embodiments, directional representations—i.e., up,down, left, right, front, rear and the like, used for explaining thestructure and movement of the various elements of the PresentApplication, are relative. These representations are appropriate whenthe elements are in the position shown in the Figures. If thedescription of the position of the elements changes, however, it isassumed that these representations are to be changed accordingly.

The Present Application describes a low impedance interconnection systemoperably placed between the two substrates whereby the interconnect iseither placed to one side of the device or devices or the interconnectsystem circumferentially surrounds these elements.

When a load change occurs in operation on one of these devices, avoltage will occur across the interconnect that can be described asshown below:

DELTA. .times. .times. V=L .times. .differential. I Step .differential.t+RI Step

wherein .DELTA. V is the voltage across the interconnection system, L isthe series loop inductance of the interconnect, R is the interconnectresistance, and I.sub.step is the step-change in load current.

As shown above, the output voltage change .DELTA. V increases linearlywith the loop inductance L. Further, where rapidly changing currents areinvolved (as is the case with step changes in current, it is criticallyimportant that the interconnect system provides for a low inductancebetween the two substrates. During such a current step, reducing theloop inductance L reduces the .DELTA. V that results from currentchanges, thus allowing power to be efficiently delivered from thecurrent source to the load.

FIGS. 1A and 1B are diagrams illustrating a structure 10 which providesa power path from a power conditioning circuit to a high performanceelectronic power dissipating device via a plurality of paths, thusyielding very low impedance. The structure 10 comprises a main boardassembly 14, an electronic assembly 13 having a high performanceelectronic power dissipating device, a power conversion assembly 12 anda heat dissipating assembly 11.

The electronic assembly 13 comprises a power dissipating device such asa microprocessor 134 assembled onto printed circuit board (PCB) orsubstrate 130 (hereinafter, the terms “printed circuit board”, “circuitboard” and “substrate” are used interchangeably). The circuit board 130includes one or more circuit traces which deliver power to the die ofthe microprocessor 134. The circuit board 130 also includes circuittraces which route signals to a matrix of pins 131 communicativelycoupled to microprocessor 134 I/O connectors. The microprocessor 134 istypically provided with a thermally conductive lid 133 in which theinside surface of the lid is in close thermal contact with the top ofthe die of the electronic device and the perimeter of the lid is sealedand attached to the surface of the substrate 130. Although the packagedescribed herein is provided with a lid the Present Application does notpreclude the use of unlidded package construction methods.

The signal pins 131 engage with a socket 141 which is mounted to a mainboard 140 both of which are a part of main board assembly 14. Signalsfrom the main board assembly 14 are dispersed to other electronicdevices to form a complete operating unit such as a computer. Othermethods may be employed to route the signals from the substrate 130 tothe main board 140 which may not utilize either pins or sockets.

The circuit board 130 includes a plurality of contacts 132. The contacts132 can include power contacts and/or ground contacts. The power andground contacts are communicatively coupled to power connectors or pads135-137 of the power dissipating device 134, respectively.

FIGS. 1C-1E disclose several embodiments of the Present Applicationshowing different electrical arrangements of the contacts 132. In oneembodiment, the power contacts include positive polarity power contacts132A that are communicatively coupled to a positive polarity powerconnector or pad 135 on the power dissipating device 134 and negativepolarity power contacts 132B that are communicatively coupled to anegative polarity power connector or pad 136 on the power dissipatingdevice 134. The ground contacts 132C are communicatively coupled to aground connector or pad 137 of the power dissipating device 134.

In one embodiment of the Present Application (illustrated in FIGS. 1Dand 1E), the power contacts 132A and/or 132B are interleaved with theground contacts 132C. In FIG. 1D, each power contact 132A and/or 132B isadjacent a ground contact 132C, and each ground contact 132C is adjacenta power contact 132A and/or 132C. In another embodiment of the PresentApplication, the positive polarity power contacts 132A are interleavedwith negative polarity power contacts 132B in the same way. Theforegoing interleaved or alternating design substantially reducesundesirable electrical impedance of the power path.

In the embodiments shown in FIGS. 1A and B, the contacts 132 aredisposed around the perimeter of the electronic device and are a part ofthe substrate structure 130.

The substrate 130 generally comprises a number of conductive layers thatare used to route both signals and power and ground. When routing power,layer pairs adjacent to each other form a very low electricalinterconnect impedance between the power pads 132 and the die powerand/or ground connectors (e.g. pads) of the electronic device 134. Theselayer pairs are connected to the power pads 132 in a closely coupledarrangement to the planes. A further description of the conductivelayers and their arrangement with respect to the z-axis compliantconductors 124 is presented in conjunction with FIGS. 3A-3C below.

A power conversion assembly 12 is disposed directly above (along thez-axis) the electronic assembly 13. This assembly 12 comprises aninterconnect substrate commonly referred to as a printed circuit board(PCB) 120, a power conversion circuit having components 121 such asswitching transistors, transformers, inductors, capacitors, and controlelectronics; output capacitors 123 and a compliant conductor assembly122 having a plurality of z-axis compliant conductors 124. These powerconversion components can be segmented according to the VRM circuittopology to optimize the impedance and power flow through the powerconditioning circuitry. For example, in the case of a multiphase VRM,the topology of the VRM can be designed to provide one or more of thephases, each at the appropriate connector, thus minimizing theinterconnect impedance and the required circuit board real estate. Theplurality of z-axis compliant conductors 124 circumscribe and interfacewith the contacts 132 on the electronic assembly 13 to provide aconductive path between the power conversion assembly 12 and theelectronic assembly 13 having very low inductance. Further, theconductor assembly 122 permits the power conversion assembly 12 and theelectronic assembly 13 to be disassembled and separated withoutdesoldering.

A significant advantage to injecting power to the power dissipatingdevice in a circumferential manner is that the current in any portion ofthe power planes of the substrate used to deliver power to the powerdissipating device can be reduced significantly. As an example, if fourcompliant contact assemblies are located on each of the four sidesadjacent to the power dissipating device, then, the maximum planecurrent is one-quarter the total current of the device assuming that thecurrent in the device has a uniform current density at its interface tothe substrate. Furthermore, the path length is significantly lower thanother methods to deliver power to the substrate further reducing thevoltage drop in the power delivery planes of the substrate (see, forexample, U.S. Pat. No. 5,980,267, which is hereby incorporated byreference herein). Generally, the power delivery regulation budget isfixed and the power planes of the power dissipating device substrate areadjusted to maintain the desired budget either by increasing the numberof planes or increasing the thickness of the planes as the current isincreased or the budget is decreased. Circumscribed power deliveryprovides for significant reductions in both plane thickness and/or totalnumber of planes.

In the illustrated embodiment, the conductors 124 of the conductorassembly 122 are attached (e.g. soldered or bonded) to the substrate120. Further, the conductors 124 of the conductor assembly 122 areelectrically coupled to the contacts 132 of substrate 130 throughmechanical pressure applied to urge the substrate 120 towards thesubstrate 130.

Other variations of this structure are possible. As an example, thecompliant conductor assembly 122 could be permanently attached tosubstrate 130 with contact pads on substrate 120 or, contact pads couldbe place on both substrates 120 and 130 and the compliant contact couldprovide pressure contacts to both substrates. Note that some of theinterconnect compliant contacts may be used for control and senseinterfaces between the power circuitry in assembly 12 and the electronicassembly 13. Finally, note that substrate 120 has an aperture to allowfor the lid 133 to pass through and thermally couple to the heatsinkassembly 11.

In the past, it has been necessary to position bypass capacitors onsubstrate 130 to provide for the transient current demands of theelectronic device on the substrate. This has reduced the reliability ofthe electronic assembly 12 which is relatively much more expensive thanthe other assemblies. Thus, it is desirable to increase the reliabilityof this assembly to the highest degree possible. Because theinterconnect inductance of the compliant contacts 122 is extremely lowit is possible to position the necessary bypass capacitors 123 on thepower conversion substrate 120. Further, note that these capacitors 123are located directly above the conductor assembly 122 reducing theinterconnect path length between the connector and the capacitors 123(thus decreasing the impedance) to approximately the thickness of thesubstrate 120.

Heatsink assembly 11 is used to remove heat from both the electronicassembly 13 and the power conversion assembly 12. Heatsink assembly 11comprises a finned structure 100, which is attached or is a part of base111. Heat slug or mesa 112 is attached to or is a part of base 111 andis used to both disperse heat from the lid 122 and to mechanicallyconform to the proper vertical displacement between the lid of themicroprocessor 134 and the heat sink base 111. Thermal interfacematerials may be used to thermally couple the lid 133 and the mesa 112to the heatsink base 111 and the substrate 120/power components 121. Theheatsink base 111 may also comprise cavities to accommodate anycomponents on the top side of substrate 120 such as capacitors 123.

FIGS. 2A and 2B illustrate a structure 15 which is similar to structure10 except the power conversion circuit components are located directlyon the main board assembly 18. The structure comprises the main boardassembly 18, a high performance electronic assembly 17 and a heatdissipating assembly 16.

Electronic assembly 17 is similar to electronic assembly 13 withsubstrate 170, lid 171 and pin matrix 172. However, contacts 173, whichcan be used as power pads, are located on the bottom side of substrate170. In the illustrated embodiment, the contacts are disposed around theperimeter of the electronic device 172.

Main board assembly 18 comprises a main board 180 with power conversioncomponents 181 making up a power conditioner circuit and compliantconductor assembly 182 having a plurality of z-axis compliant conductors185 circumscribing a socket 183. As was the case with assembly 13,bypass capacitors 184 are placed on main board 180 directly under and inelectrical communication with the z-axis compliant conductors 185. Heatsink assembly 16 is disposed above and is thermally coupled to theelectronic assembly 17. The heat sink assembly 16, which removes heatfrom the electronic assembly 17, comprises a finned structure 160 andbase 161.

Thermal interface material can be used between the base 161 and the lid171 to thermally couple the base 161 and the lid 171. Thermal energy mayalso be removed from the power conversion components 181. This can beaccomplished by providing a thermal conduction path from the bottom ofthe main board to an adjacent chassis surface. This can also beaccomplished by simply providing sufficient airflow around thesecomponents so as to directly cool them. It is also noted that as was thecase with the embodiments illustrated in FIGS. 1A and 1B, where ultimateelectrical performance is not needed, compliant conductor assembly 182and power components 181 may not need to circumscribe socket 183 and maybe located on less than all four sides of socket 183.

FIG. 2C is a diagram of a structure 15 that is similar to that shown inFIG. 2A except that compliant conductor assembly 182 are at leastpartially enclosed and contained within the socket 186 which mounts tothe main board 180. This facilitates the assembly of main board assembly18.

FIG. 2D is a diagram presenting a section view (A-A) along one side ofsocket 186 showing the socket 186 and the compliant conductor 182. Thesocket 186 includes a section 186A that secures individual z-compliantconductors 182 in place by overmolding a base extension 187 of theconductors 182. Socket 186 includes a plurality female connectors 193which accept pins that are communicatively coupled to the powerdissipating device. Each female connector is also communicativelycoupled to solder balls, which are reflow soldered to circuit pads 190on main board 180. The power dissipating device is thus electricallyconnected to the main board 180, which, as shown in FIG. 2C, includespower components 181 for power conditioning.

The base 192 of compliant contact 182 is soldered to power contact pad189. This is preferably accomplished during the same reflow solder stepused to couple the solder balls 191 to the circuit pads 190 on the mainboard 180. Not shown are power connection paths to internal layers ofmain board 193 from surface contact 189.

FIGS. 3A-3C illustrate an embodiment of a stackup 30 configured todeliver power from a power conversion PCB 301 to a processor substrate300. It will be recalled that a preferred embodiment of power deliveryis to deliver power through alternating or interleaved contacts so as toreduce the interconnect impedance.

FIG. 3A is a diagram showing a plan view of the stackup 30 with theupper PCB 300 removed, showing the arrangement of adjacent z-axiscompliant conductors 305 and 321 in the x-y plane. In one embodimentillustrated, the conductors are spaced approximately 50 mils apart, todecrease impedance. Further, the illustrated z-axis compliant (or,equivalently, compliant) conductors 305 and 321 are cantilevered beamshaving bases that are soldered or other wise affixed to contacts (orcircuit pads) 303 and 320, respectively. The other end of the compliantcontact is pressed against the contact. (or circuit pad) of the uppercircuit board 300.

FIG. 3B is a diagram illustrating a cross section (A-A) of one polarityof power delivery, e.g., the positive polarity, while FIG. 3Cillustrates a cross section (B-B) of the negative polarity, the twosections adjacent to one another forming the preferred interleavepattern.

Referring to FIG. 3B, power conversion PCB 301 contains power layers 312and 313 wherein layer 312 represents the negative power layer, and layer313 represents the positive power layer the two of which are in closeproximity to one another to effect a low impedance power interconnect. Aplated through hole (PTH) 314 or similar conductor connects the positivepower layer 313 to a surface pad 303. Z-axis compliant contact 305 isshown as a cantilever beam having a base that is soldered 304 to surfacepad 303. The other end of the compliant contact 305 is pressed againstcircuit pad 302 on the surface of the substrate 300. A bypass capacitor322 is located below the compliant contact 305 and on the side of thefirst circuit board 301 opposite contact 303. The bypass capacitor 322includes first and second connectors such as conductive end metalizationfeatures 306 and 317, which are surface mounted and electrically coupledto pads 307 and 316, respectively on PCB 301. Circuit pad 307 isconnected to layer 313 through an extension of PTH 314. Circuit pad 316is connected to layer 312 through an inter-connector such as theillustrated blind via 315. Preferably, the bypass capacitor 322 isdisposed directly below the compliant contact and associated structure(e.g. displaced from the structure in substantially only the z-axis); asthis offers lower inductance than embodiments where the bypass capacitor322 is displaced laterally (in the x and/or y axes as well).

In the illustrated embodiment, layer 308 of substrate 300 is assigned anegative power polarity while layer 309 of substrate 300 is assigned apositive power polarity Like layers 312 and 313, in the PCB 301, layers308 and 309 are in close proximity to one another to achieve a lowimpedance power interconnect. A power dissipating device located onsubstrate 300 can therefore receive power through layers 308 and 309 ofthe substrate 300. Circuit pad 302 is electrically connected to layer309 through one or more blind vias 310 thus forming a low impedanceinterconnect from layer 313 through PTH 314 to pad 303 then throughcompliant contact 305 to pad 310 and then through blind vias 310 tolayer 309. Note that layers 308 and 309 are located on or near thesurface of substrate 300. This frees the substrate 300 to use the otherlayers (represented as layers 311) for signal interconnect for the powerdissipating device without topological complications that arise fromdesigns in which the power and ground layers are disposed away from thebottom surface of the substrate.

Referring again to FIG. 3C, (which illustrates a cross section (B-B) ofthe negative polarity, thus forming the preferred interleave patternwith the cross section A-A in FIG. 3B) the negative polarity powerinterconnect is achieved by PTH 319 connecting layer 312 to surfacecontact (e.g. pad) 320 adjacent the positive polarity surface contact orpad 303 on the inner side of PCB 301. Compliant contact 321 is soldered304 or otherwise coupled to surface pad 320 while the other end of thecompliant contact 321 is pressed against (surface) layer 308 ofsubstrate 300. Note that contact point for compliant contact 321 isshown as a point (or more specifically, a line segment along the y-axis)on layer 308 however, this contact area may be a unique area of layer308 in which the surface is locally processed to provide specialcharacteristics for this contact point such as gold plating over anickel undercoat to improve the contact characteristics of the contact.Surface pad 310 may be processed in a similar manner.

Finally, capacitor 322 may be the same bypass capacitor as shown in FIG.3B or an additional bypass capacitor connected to planes 312 and 313through an extension of PTH 319 to surface pad 316 and blind via 318 tosurface pad 307. The result of the above is to provide a very lowcompact and low inductance compliant connection between PCB 301 andsubstrate 300 with the two substrates being separable. Furthermore,because the interconnection method provides for a very low inductanceconnection it is possible to either eliminate or considerably reducebypass capacitors on the substrate 300 containing the power dissipatingdevice.

Because such substrates are constructed such that the interconnectsbetween layers 308 and 309 are blind vias 310 which pass only betweenlayer to layer and not through the entire substrate, signal layers 311and additional power/ground layers (if any) will not be permeated withlarge numbers of via interconnects (such as 310) as would be if powerentered from the top side of substrate 300. This has the benefit offreeing up signal routing space in these layers (such as 311) where thenumber of via interconnects are substantially reduced due to theentrance of power to the bottom side of substrate 300.

The embodiment shown in FIGS. 3A-3C is superior to other interconnectdesigns wherein the capacitor is not placed below the z-axis compliantconductors and on the opposing side of the circuit board with the powerconditioning circuitry. For example, if the capacitive element wereplaced on the second side of the first circuit board (the same side asthe z-axis compliant conductor) and adjacent to the spring members, thelength of the conductive path and hence the impedance of theinterconnect would include not only the vias or PTHs traversing in thez-axis, but also traces or planes in the x-y plane. By placing thecapacitive element 322 on the side of the circuit board opposing thez-axis compliant conductor and directly over (or under) the z-axiscompliant conductor, the length of the conductive path (and hence theimpedance) is substantially reduced. The conductive path length (andhence, the impedance) is further reduced by selecting the span of thecapacitive element 322 and related structures (e.g. pads 307 and 316) tobe substantially the same as the span (the length in the longitudinal,or x-axis, direction) of the z-axis compliant conductor. With the lengthof the conductive path minimized capacitive elements on the secondcircuit board (or substrate) can be removed, which improvesmanufacturability and reliability as well.

FIGS. 4A and 4B illustrate an isometric view of one embodiment of aU-shaped z-axis compliant conductor 40. The conductor 40 comprises abase 401 which can be soldered or otherwise bonded to a substrate whilecontact surface 400 is pressed against a pad on an opposite substrate.FIG. 4A shows the conductor 40 in the uncompressed state while FIG. 4Bshows the conductor in the compressed state. In the illustratedembodiment, the contact surface 400 is formed by an S-shaped portionhaving a curved surface. The curved surface assures that the conductor40 presents a surface parallel to the circuit board above the contact40.

FIGS. 5A and 5B illustrate an isometric view of another embodiment ofthe z-axis compliant conductor 50. The conductor has a base or firstshaft portion 502 having a first end 504 and a second end 506 distalfrom the first end 504. The base 502 is generally soldered to asubstrate contact. A U-shaped bend portion 508 is coupled to the firstshaft portion 502. The U-shaped bend portion 508 includes a first end510 adjacent and coupled to the first shaft portion second end 506 and asecond end 512. A second shaft portion 514 is coupled to the U-shapedbend portion 508. The second shaft portion includes a first end 516adjacent and coupled to the U-shaped portion second end 512. Secondshaft portion is adjacent and coupled to a second U-shaped bend portion520. The second U-shaped bend portion comprises a first end 522 adjacentand coupled to the second end 518 of the second shaft portion 514 and asecond end 524. The second U-shaped bend portion is adjacent and coupledto a third shaft portion 526 disposed between the first shaft portion502 and the second shaft portion 514. The third shaft portion 526includes a first end 528 adjacent and coupled to the second end of thesecond U-shaped bend portion 520 and a second end 530 distal from thefirst end 528. Bend portion 532 is disposed at the second end 530.

The conductor contact surface 534 is pressed against a pad on anopposite substrate. The contact beam is then wrapped around and returnsto the upper surface of base 502 forming a secondary contact 536 to thebase 502. This embodiment has improved (reduced) connection inductancecompared to the embodiment illustrated in FIGS. 4A and 4B because themutual coupling between path 538 and path 540 is relatively low whichestablishes semi-independent and parallel connection paths betweencontact surface 534 and the base 502.

FIGS. 5C and 5D illustrate an isometric view of still another embodimentwhich is similar to that described in FIGS. 5A and 5B. FIG. 5Cillustrates this embodiment in the uncompressed state whereas FIG. 5Dillustrates the embodiment in the compressed state. This embodimentfurther comprises a third u-shaped bend portion 557 coupled to thedistal end 530 of the third shaft portion 526, a fourth shaft portion555 coupled to the third u-shaped bend portion 557. The fourth shaftportion 555 includes a contact portion 556 distal from the thirdu-shaped bend portion 557. When compressed, the contact portion 556establishes an additional third path between the contact point 552 andthe base 502 that passes through the fourth shaft portion 555, the thirdu-shaped bend portion 557 and to the base 502. This embodiment has stillfurther reduced inductance over the embodiment in FIGS. 5A and 5Bbecause there are now three semi-independent paths 551, 553 and 555between the contact surface 552 and the base 550.

Individual conductors can be grouped so as to ease assembly of theconductor onto a PCB or substrate using soldering or other joiningprocesses. One method is to extend a surface feature (such as 401) ofthe conductor to an area outside of the active portion of the conductorwhich is joined to a common bar during the stamping and formingfabrication process and then to overmold this extended feature with aninsulating plastic resin up to the common bar but not including the bar.The bar is then cut off leaving a set of individual isolated contactsthat are mechanically joined and can be handled during assembly as oneunit.

FIGS. 6A-6C illustrate another embodiment of the Present Application inwhich z-axis compliant conductors similar to those shown in FIGS. 5A and5B are arranged in a scissor configuration.

FIGS. 6A and 6C illustrate an isometric view of the assembly 60 showingpairs of z-axis compliant conductors 600A, 600B, 600C, 600D (hereinafteralternatively referred to as first set or row of z-axis compliantconductors 600) and 601A, 601B, 601C, 601D (hereinafter alternativelyreferred to as second set or row of z-axis compliant conductors 601).Each of the conductors in each row 600, 601 of the assembly 60 comprisesan interface portion 668 and 669 disposed away from the base of theconductor that is urged against the contact on the second circuit board.Further, each row 600, 601 of assembly 60 is preferably assigned aseparate power polarity, e.g., row 601 might be assigned negative powerpolarity and row 600 might be assigned a positive power polarity. Theconductors of the first row 600 and the second row 601 are therebyinterleaved to form conductor pairs resulting in a low inductance powerpath.

Each of the conductors 600, 601 are held in place by an assembly such asovermold frame assembly 602 having an outer portion 602A and an innerportion 602B. In the illustrated embodiment, the assembly holds thez-axis compliant conductors in place about at least a portion of theperiphery of the power dissipating device. Hole 667 is an alignmentfeature that may be desirably placed in the molded assembly 60 to alignthe assembly 60 to the PCB (e.g. PCB 120) during soldering.

FIG. 6B illustrates an isometric View of a pair of spring contacts 600A,601A in the scissor configuration. The base 612 of each contact in therow of contacts is extended to overmold 602 as described in thepreceding paragraph to simplify assembly. In this arrangement, overmoldouter portion 602A and overmold inner portion 602B are desirably joinedat their respective ends to form the overmold assembly. An advantage ofthis configuration is that there is no resulting net torsional forceabout the y or z axes.

FIG. 6C is a section view (section A-A illustrated in FIG. 6A)presenting an example where the scissor contacts described above arearranged in a stackup 61 to deliver power from a power conversion PCB608 to a processor substrate 609. The circuit pads 610 on PCB 608require isolation between adjacent pads in the y-direction, because theywill have alternating positive and negative power polarities. However,of significant importance is that contacting pads 605 and 606 on theprocessor substrate 609 can be arranged to be a continuous linear pad inthe y-direction. This provides for relaxed tolerances in the alignmentof the processor substrate 609 to the power conversion substrate 608 orPCB, and reduces the net torsional force on the two substrates. Notethat bypass capacitor 607 may be installed beneath the contactarrangement 61 in a manner similar to that as described in FIG. 3.

One technique of reducing the effective inductance of a multi-conductorconnector is to assign adjacent conductors opposing current polarities.The magnetic fields of the opposing currents partially cancel eachother, thus reducing the effective inductance of the overall connection.However, the effectiveness of this configuration is strongly dependentupon the configuration of the multiple conductors. In a simpleconfiguration wherein the opposing faces of adjacent conductors arerelatively narrow compared to their separation, the magnetic couplingbetween the conductors does not provide a substantial amount of magneticfield cancellation. However, if the separation distance between thesubstrates in a parallel plane connection scheme such as illustrated inFIG. 6C is small relative to the width of the conductors, then themagnetic field coupling between the planes becomes more significant,thus resulting in a lower inductance. This effect can be enhanced byarranging the conductors in each row 600, 601 of the connector in anopposing configuration as shown in FIG. 6B. Then, the current from onepair of conductors (e.g. 600A and 601A) now flows across each end of theconnector bases and in internal planes of the substrates 608 and 609.This current magnetically couples with the current flowing in thenon-base portions of the scissored conductors (600A and 601A), reducingthe overall inductance of the connection between substrates 609 and 608.For the effective inductance of this scissored arrangement to be lessthan the effective inductance of a non-scissored arrangement, the anglethat the conductors make with the PCB/substrate plane must be less thana particular value .theta.=f(t, w, s) wherein t is the conductorthickness (here, assumed uniform), w is the width (also assumed uniform)and s is the separation between adjacent conductors.

FIG. 6D is a plan view of substrate 609 further illustrating the conceptof the continuous pads 605 and 606 that surround power dissipatingdevice 613. In the illustrated embodiment, the pads 605 and 606 areformed into a continuous rings, one inside the other.

FIG. 6E illustrates a variation on the scissor contact design describedin FIGS. 6A-6C. A base portion 670 of an elongated z-axis compliantconductor 630 (of a scissor pair) is soldered to pad 632 on PCB 608. Theupper cantilevered beam portion 634 of compliant conductor 630 ispressed against contact pad 631 of substrate 609 as previouslydescribed. However, in this configuration, rather than the secondarycontact wrapping around and returning to the top surface of the base502, the contact 630 wraps around portion 635 of compliant conductor 630returning to a separate contact pad 633 on PCB 608. Although bothcontact pads 632 and 633 are in electrical communication with the samepower conditioning circuit, (e.g. through vias and conductive layers inthe substrate 609) the advantage of this configuration is that themating surfaces 636 of contact pad 633 and contact portion 635 are notinvolved in the soldering process and as a consequence there is no riskthat solder used to couple the base 670 of the conductor 630 to the pad632 may flow into the contact region of the secondary contact 633.Additionally, because the secondary contact is further removed from theinitial contact path there is less mutual coupling between the twocontact paths which results in a lower overall connection inductance.

FIG. 6F illustrates another embodiment of the Present Application. Inthis embodiment, the stackup configuration 64 includes a first andsecond set of U-shaped z-axis compliant conductors (640 and 641,respectively) that are displaced from one another along the x-axis. Thex-axis displacement allows contact pads 644 and 645 to be constructed ina continuous linear fashion on substrate 609 similar to the embodimentshown in FIGS. 6A, 6B and 6C, without requiring that the first andsecond set of conductors 640, 641 be oriented 180 degrees from eachother. Z-axis compliant conductor 640 is soldered or otherwise connectedto contact pad 642 on PCB 608 which is connected to one polarity of apower circuit (e.g., as shown in FIGS. 3A-3C) while z-axis compliantconductor 641 forward of conductor 640 and displaced from conductor 640in the x-axis is also soldered or otherwise electrically coupled tocontact pad 643 of a second polarity of a power circuit (also as shownin FIGS. 3A-3C).

The embodiments illustrated in FIGS. 6A-6F have numerous advantages.First, as described above, they permit substantial misalignment betweenthe z-axis compliant conductors and the contacts on the opposing circuitboards in the direction of the adjacent conductors (e.g. in the y-axisdirection in FIGS. 6B-F). Second, a nearly contiguous line of viasdisposed through the pad region can be used for connecting the contactsto conductive planes within the circuit board, thus allowing a lowerinterconnect impedance in the substrate 609. Third, as described furtherbelow with respect to FIGS. 6I and 6J, the arrangement shown in FIGS.6A-6C allows for improved electromagnetic coupling between each springover arrangements where each of the z-axis compliant conductors arearranged in a single row.

FIG. 6G illustrates a stackup configuration 65 in which the z-axiscompliant conductor is removably attached (e.g. not soldered, bonded, orotherwise permanently attached) to either substrate 609 or PCB 608. Inthis configuration insulating (plastic, for example) overmold element652 retains compliant conductor 651. Additional conductors (disposed inthe y direction) are also retained by plastic element 652, forming acontact assembly that can be installed at the time of assembly ofsubstrate 609 and PCB 608. As before, section 653 of compliant conductor651 is pressed against contact pad 605 on substrate 609 and section 654is pressed against contact pad 655 of PCB 608 completing one half of apower circuit between PCB 608 and substrate 609. The other half of thepower circuit is completed by the adjacent conductor (displaced fromconductor 651 in the y-axis). It is also recognized that an arrangementsuch as that which is shown in FIGS. 6F and 6G may also be applied in asimilar manner as to the arrangement in FIG. 6C, with opposing orstaggered conductors, using a multiple-part or shaped overmold.

FIG. 6H illustrates still another arrangement wherein a compliantconductor may be used to provide power to a power dissipating device. Inthis arrangement, the plurality of first circuit board contacts 664 aredisposed on the edge of the first circuit board. While only a singlecontact 664 is shown, a plurality of contacts, electrically isolatedfrom one another and distributed in the y-axis, are disposed on the edgeof the first circuit board 609. Section 661 of each of the x-axiscompliant conductors 660 is urged against an adjacent side contact 664which is electrically connected to internal conductive plane 662 ofsubstrate 664. The internal conductive plane 662 is electrically coupledto the power dissipating device (via conductive planes, vias, and thelike) to feed power to a power dissipating device disposed on thesubstrate 664. The other end of conductor 660 is soldered or otherwiseelectrically connected to contact pad 665 of PCB 608. Electricalconnection between the contact pad 665 and to power layers of the PCB608 can be made by a combination of plated through holes, vias andinterconnecting conductive layers in the PCB 608.

Only one contact is shown in the section view of FIG. 6H. However, itwill be understood that a multiplicity of compliant contacts 660 can bearranged along the y-axis and the multiple compliant contacts 660 caninterface with a corresponding multiple of edge contacts 664, eachelectrically isolated from the others, to form multiple powerconnections between PCB 608 and substrate 664, wherein alternatingcontacts 664 connect to alternate polarity power plane 663. In apreferred embodiment, the contacts 660 and related structurescircumscribe all sides of substrate 664 to form a very low impedancepower interconnect path between PCB 608 and substrate 664. The conductor660 can also be designed with a bend to restrain the first circuit board609 in place, if desired.

FIG. 6I illustrates one embodiment of the z-axis compliant conductordesign. The illustrated z-axis compliant conductor pair which form apart of a larger array of conductors. Conductor 671 carries current inof one polarity while adjacent conductor 672 carries current in anopposite polarity. As before, a practical method of assembling such anarray is to join the individual conductors with an overmolded plasticresin 673 that supports the conductors 671 and 672. Of note is that eachof the conductors 671 and 672 are provided with a slit 677 and 680 whichcreates two separate current paths in conductors 671 and 672 over asubstantial portion of the length of the conductors. These separatecurrent paths are identified as 675, 676 for conductor 671 and 678 and679 for conductor 672. The result of this arrangement is to reduce theoverall connection inductance between a PCB and a substrate.

The reduced connection inductance of FIG. 6I can be explained byreferring to FIG. 6J which illustrates a section view through theconductor sections as indicated by A-A. The top portion of FIG. 6Jillustrates the arrangement where there is no slit, forming conductors681 and 682, whereas the bottom portion illustrates the arrangementwhere the slits 677 and 680 form conductors 685, 686, 687 and 688. Theinductance of each conductor, 681 or 682, in the configuration withoutthe slit is:

L 681, 682=2 ln .times. S .times. .times. 1 0.2235 (t+W .times. .times.1)

For the configuration with the slit 677, 680, the inductance of the pairof conductors 685 and 686 or 687 and 688 can be determined bycalculating the inductance of each conductor and then noting that theconductor pair are in parallel with one another. The general equationfor the inductance of a multi-conductor configuration where the currentin all conductors is equal (this is the case since, by symmetry, acontinuous set of paired contacts as shown in FIG. 6I must have the samecurrent in each path) is:

1=2 ln .times. GMD GMR .times. 10-7

where GMD is the geometric mean distance from the first group ofconductors to the second group of conductors and GMR designates thegeometric mean of the individual geometric mean radii of the grouptogether with the wire-to-wire distances among the conductors of thatgroup. Applying the forgoing relationships yields an expression for theinductance of the conductors 685, 688, 686, 687 is as follows:

L685, 688=.times. 2 ln .times. (S .times. .times. 2+S .times. .times.3).times. (S .times. .times. 2+2 S .times. .times. 3) 0.2235 (t+W.times. .times. 2) S .times. .times. 3.times. 10-7 L 686 , 687=.times.21n .times. S .times. .times. 2 (S .times. .times. 2+S .times. .times.3) 0.2235 (t+W .times. .times. 2) S .times. .times. 3.times. 10-7

The pair inductance then is simply L.sub.685,688 in parallel withL.sub.686,687:

L pair=L 685, 688 L 686, 687 L 685, 688+L 686, 687

When the above equations are applied to practical conductor geometries,substantial reductions in inductance can be achieved by providing a slotin the contact arrangement as shown in FIG. 6I.

It is understood that in all of the previously described conductorembodiments, it is important to design the contact arrangement such asto avoid rotational forces that may be imparted to the base of thecontact wherein the base is soldered to one of the substrates. Thereason for this is to eliminate normal forces that are not incompression (along the z-axis) which apply a torsional force to the baseportion of the conductor, and which may result in solder creepage, andultimately the failure of the solder joint between the base of theconductor and the substrate pad. This can be accomplished by designingthe conductor so that the interface portion that contacts the secondcircuit board contact and the base portion that contacts the firstcircuit board contacts are disposed substantially only along the z-axisfrom one another (e.g. either above or below each other, but notdisplaced in the x-y plane). This can be achieved, for example asdemonstrated in the foregoing description where the compliant conductorbeam is folded over the base of the conductor.

It is also desirable to design the conductor and contacts tocooperatively interact with each other to minimize contact resistanceand insure good electrical connection. This can be accomplished, forexample, with the S-shaped conductor portions (such as that which isillustrated in FIGS. 4A and 4B, or other electrical contact-enhancingdesigns).

FIG. 7 is a diagram illustrating a plan view (looking up into PCB 120)of another embodiment of the Present Application. As in previousembodiments, the z axis compliant conductors, as well as the contacts onthe PCB and substrate that interface with the z-axis compliantconductors are disposed about the periphery of the power dissipatingdevice. Further, the power and ground (or positive and negative power)conductive paths formed by the conductors and contacts were interleavedto reduce inductance. In the embodiment illustrated in FIG. 7, the setcontacts on the first circuit board and the set of contacts on thesecond circuit board are separated into two subsets of contacts, and thez-axis compliant conductors are separated into two subsets of conductorsas well. As was the case in the embodiments discussed previously, thefirst subsets of the contacts on the first and second circuit boards andthe z-axis compliant conductors are disposed circumferentially aroundthe power dissipating device. However, in this embodiment, the secondset of contacts on the first and second circuit boards and the z-axiscompliant conductors are disposed circumferentially around the firstsubset of contacts on the first and second circuit boards and the z-axiscompliant conductors. The result is two “rings” of circuit paths fromthe first circuit board, through the first subset 122A and the secondsubset 122B of z-axis compliant conductors, to the second circuit board,wherein each ring includes a plurality of interleaved ground and powerpaths. The multiple “rings” of contacts 122A and 122B, one behind anddisposed circumferentially about the other, are used to achieve evenlower interconnect impedance between the PCB 120 and the substrate 130.This is accomplished at least in part because each of the multiple rowsof contacts 122A and 122B effectively couple in parallel.

One of the advantages of the Present Application is that it permitssimplification of the power/ground/signal interconnect between relatedprinted circuit boards. FIG. 8 is a diagram illustrating a typicalstackup arrangement 5 having power/ground/signal interconnect contentionproblems. The substrate 847 of the stackup 5 includes conductive circuitlayers 831, 834, 836, 839, and 841, and insulating layers (832, 835,837, 840, and 842) reside between the circuit layers 831, 834, 836, 839,and 841. A surface layer 826 typically is used for making contactthrough bumps to power dissipating device 827. The number of insulatingand conducting layers may be increased or decreased depending upon thesignal and power demands of the power dissipating device.

In most integrated circuit packages, power enters from pins 845 disposedon the opposite side of the power dissipating device 827 and isdistributed through power vias 833, 838 in the substrate 847. The powerdissipating device 827 has connectors for power and ground (828, 829shown) which connect to a surface layer 826 of substrate 847. To ensurea low impedance DC power distribution path, multiple power vias 838 andground vias 833 must pass through substrate 847 to connect with multiplepower and ground pins (e.g. 844 and 843 respectively). Power and groundis distributed from contacts 845 including lower contacts 844 and 843(which may be a large numbers of pin connections in a socket).

Power contacts 844 are coupled to one or more power planes 841 and 836by one or more power vias 838, 848, and thence to power bumps 829.Similarly, ground contacts 843 are coupled to one or more ground planes839, 834 by one or more ground vias 849 and thence to ground bumps 828.Signal contacts, e.g., 830, connect to conductive signal layers 831 andthen typically distribute signals to the periphery of the device throughsignal vias, e.g., 825, and then down into a signal contact, e.g., 846,for distribution to other components communicatively coupled to thecontact 846 (for example, a motherboard).

FIG. 9 is a diagram of an improved power distribution systemconfiguration 90 in which power taps 901 are provided through the topside of substrate 923 instead of through the bottom. Power taps 901represent where the compliant conductors make contact to the pads on thetop surface of the substrate to distribute power from a power source tothe power dissipating device 906 on substrate 923. Power dissipatingdevice 906 on substrate 923 is connected as described in FIG. 8, exceptthat that power layer 908 does not require substantial via distributionsto lower layers such as layers 912 arid 914. Power enters power taps 901whereby the power layer 902 connects to the right power tap 901B and theground plane 910 connects to left power tap 901A through via 903. Groundplane 910 then connects to vias 924, which in turn connect to groundbumps 905 on power dissipating device 906. Additionally, power is routedfrom power plane 902 to power bumps 904 on power dissipating device 906.This completes the power distribution path for the substrate stackup 923from the source to the load, e.g., the power dissipating device 906.Note that for illustrative purposes, the bumps 904, 905 on powerdissipating device 906 are raised slightly off of the power plane 902.

Signal connections from power dissipating device 906 may now be routedto one or more bumps 907, which connect to one or more vias 915 whichroute to one or more signal planes 917. Other signals may now bedistributed to pin connections (or alternatively other bumpinterconnects such as in an interposer to substrate connection) forconnection to pins (such as 921 through vias similar to 922) whichconnect to a socket-like interconnect or PCB. Ground connections 920through vias 919 and ground plane 914 may now be used for signalreference only rather than for power distribution as well. As in FIG. 8,insulation layers 909, 911, 913, 916, and 918 make up the rest of thesubstrate 923 construction.

This embodiment allows for a reduction in the number of layers becausethat power distribution is facilitated predominately through the top twolayers 908, 910 of substrate 923. Additionally, since the power andground conductive layers are disposed on a power dissipating device sideof substantially all of the conductive signal layers, the passage ofpower through the planes of the conductive signal layers is minimized.The distribution of signals the x-y planes is also improved. This is dueto elimination or reduction of the number of vias for power and grounddistribution in substrate 923 that would normally have been used toconnect to pins 845 as described in FIG. 8. Through elimination of thepower and ground vias in these lower layers (utilizing the top twolayers), x-y plane real estate is henceforth available for additionalsignal routing in the lower layer(s), e.g., 917.

FIG. 10 illustrates an embodiment of the Present Application wherein thepower conditioning circuit or module 1000 includes a plurality of powerconditioning submodules 1001A-1001D, which together provide a powersignal having a plurality of phases. In this embodiment, the topology ofthe power conditioning circuit 1000 delivers power to a plurality ofcompliant conductors 1003 advantageously arranged to apply differentphases of the power signal to different sides of the power dissipationdevice 1006. The power dissipation device 1006 is shown connected topower and ground planes 1005 and 1004 located on substrate 1002. It isunderstood that the power dissipation device/substrate 1006/1002 residesat a level either above or below the voltage regulation module 1000.Power and ground planes 1005 and 1004 then connect to VRM 1000 throughcompliant conductors 1003 which circumscribe power dissipating device1006 wherein the ground of each phase connects to ground plane 1004 andthe voltage out of each phase connects to the power plane 1005.

Topologically, each phase is represented by an input voltage (VIN) totwo FET switches and an L-C output circuit. In the illustratedembodiment, each phase operates 90 degrees out of phase with the otheradjacent to it. Because of the organization of the phases and due to theplacement of the compliant conductors 1003 one may lay out the PCB ofVRM 1000 in this topological fashion which improves routing andinterconnect impedance due to the partitioning of each phase about theperiphery of the power dissipating device. This allows the inductors,capacitors, and electronic drive circuitry (FETs, etc.) of each phase tobe logically placed adjacent to a linear compliant conductor 1003resulting in a superior layout and interconnect scheme which issynergistic with the topology of the VRM itself.

FIGS. 11A-11B illustrate the concept for mounting power directly to aboard with the use of power pin attachments to the substrate of thepackage. Power pins [1102, 1103] (e.g. power and ground) are attachedelectrically and mechanically to substrate 1104. Ground return 1103 is acoaxial integrated pad which is part of 1101 and also acts as thermalheat-spreader for die 1105 which is attached thermally to 1103 throughthermal interface 1106.

FIG. 11C is a blow-up section of view A-A in FIG. 11A, which expands onthe construction of the pin attachments. Power pin 1102 is mounted tosubstrate 1104 through solder or press pin 1110 which connectselectrically to inter-plane 1107 in substrate. Solder or press pin 1110is connected to plated thru-hole 1109 electrically and mechanically. Adielectric insulator 1112 isolates 1102 from 1103. The center section of1102 is threaded for attachment to the board. Additionally, taper 1111is constructed to allow an electrical joint attachment to the board.This will be explained below.

FIG. 12 illustrates a split-wedge washer and screw fastener constructiondesigned to electrically and mechanically attach sub-assembly [A] tosub-assembly [B]. Split-wedge washer 1217 is designed with a lip section1219 for forcing mechanically sub-assembly [A] to [B]. Wedge section1216 is shown along with split section 1218.

FIG. 13 shows the attachment of a section (FIG. 11C and FIG. 12combined) integrated with board 1320. The split-wedge washer engageselectrically and mechanically to the side of plated thru-hole 1322 inthe board by having taper section 1111 of 1102 spread 1217 outward toforce against [Z]. Simultaneously, screw fastener 1215 forcessub-assembly [A] against [B] by pulling 1217 against 1320 and bringingassembly [B] against 1320. Inter-power plane 1321 is attachedelectrically to plated thru-hole 1322 which connects to powerdistribution on 1320. Additionally, ground pad 1103 is attachedelectrically to bottom pad of 1320 (not shown) to complete electricalcircuit through vias which attach to ground plane on 1320 (also notshown).

FIG. 14 shows the high level assembly of [B] attaching to [A]. VRM 1424and heatsink 1423 are attached to 1320 electrically, thermally, andmechanically as described in previous literature. Thermal interface 1425attaches to 1320 thermally as also described in previous literature. EMIframe 1426 is shown for completeness.

FIG. 15 illustrates a low inductance ‘frame’ standoff sub-assembly [C].A sheet metal frame is bent and joined at one corner to form an outerground frame 1525 with solder tabs for mounting permanently to one unit(either VRM board or main board). A dielectric tape 1527 is attached tothis structure as an insulator. Inner frame 1526 is made in similarfashion to 1525 but carries positive going current (e.g. connected topositive terminal of power supply) to supply power to IC. Mounting holes1528 are supplied to mount to one side of assembly to make mechanicaland electrical connection. Due to the dimensions of the construction,and the current paths for the electrical interconnect, a very lowinductance can be achieved resulting in a low voltage drop between thepower supply and load for low frequency switching applications.

FIG. 16 is an assembled view showing the construction together in anassembly with the structure mounted to an interface board 1730.

FIG. 17 illustrates the mounting to an interface board. The purpose ofthis board is to remove any need to mount power directly to the mainboard, which can improve rout ability and cost on the main board.

FIG. 18 shows an exploded view of FIG. 16.

While the foregoing embodiment is described with respect to a four phasepower signal applied to each of a four-sided power dissipating device,the principles described above can be applied to embodiments with feweror more than four sides and power signal phases, or to embodiments withnon-polygonal configurations (e.g. circular, for example).

In summary, the forgoing discussion discloses a low impedance powerinterconnect between the power dissipating device and the power source.The impedance of the power interconnect is low in inductance andresistance throughout a wide frequency band in order to ensure that thevoltage drops across the interconnect are mitigated across it duringdynamic switching of power. It can also be seen that the interconnectshould provide large ‘z’ axis compliance. The arrangement also reducesor eliminates the need for supporting electronic components on thedevice substrate because the interconnect impedance between the powerconditioning circuit and the device can be reduced to the point whereall or most of the support electronics can be located on the substratehaving the power conditioning circuit itself.

The Present Application also significantly reduces contentious routingof power to the power dissipating device because the power interconnectimpedance is significantly lowered and can be routed to one or moresides of the power dissipating device.

Further, since the upper layers of the power dissipating devicesubstrate are used primarily for power distribution, the area onadditional layers beneath the upper layers are free for use with forsignal and other conductive interconnects. These other conductiveinterconnects can connect other interconnects or substrates beneath orabove the stackup.

The foregoing description of the preferred embodiment of the PresentApplication has been presented for the purposes of illustration anddescription. It is not intended to be exhaustive or to limit the PresentApplication to the precise form disclosed. Many modifications andvariations are possible in light of the above teaching. For example, thesubstrate contacts and compliant conductors can be disposed proximatethe outer periphery of the substrates rather than proximate the powerdissipating device as described herein. Further, the compliantconductors may be rigid instead of compliant, while still permitting thedetachable design described herein. Also, the compliant conductors canbe integrated with other assemblies such as a socket, which might beused to interconnect signals to the microprocessor. Further, more thanone linear set of contacts can be arranged to circumscribe the powerdissipating device in a manner to increase the total number of contactsproviding power and/or ground to the device, thus reducing the overallconnection inductance and increasing total current carrying capability.The z-axis compliant contacts can also be configured so as to permitacceptance of stackup height variations.

It is intended that the scope of the Present Application be limited notby this detailed description, but rather by the claims appended hereto.The above specification, examples and data provide a completedescription of the manufacture and use of the composition of the PresentApplication. Since many embodiments of the Present Application can bemade without departing from the spirit and scope of the PresentApplication, the Present Application resides in the claims hereinafterappended.

1. A method comprising: plugging a DC-to-DC converter on top of aprocessor carrier in turn secured to a motherboard; and providingsubstantially planar power and ground contacts on said converter andsaid processor carrier; and engaging said contacts on said converterwith said contacts on said carrier through a resilient interconnecthaving resilient electrical contacts.
 2. The method of claim 1,including clamping said converter onto said processor carrier.
 3. Themethod of claim 1, including forming power and ground regions of thecontacts of said processor carrier and said converter andinterdigitating said power and ground regions.
 4. The method of claim 1,including plugging said converter into said processor carrier.
 5. Themethod of claim 1, including providing compressible contacts in saidinterconnect and compressing said contacts between said converter andsaid carrier.
 6. The method of claim 5, including maintaining electricalcontinuity through said interconnect via said electrical contacts andaligning said contacts on said converter to said carrier by inserting atleast one pin through said interconnect and said converter.
 7. A methodcomprising: attaching a processor carrier to a motherboard by movingsaid processor carrier onto said motherboard in a direction having acomponent transverse to the surface of said motherboard; and securing aDC-to-DC converter to the processor carrier in a direction having acomponent transverse to the surface of said motherboard.
 8. The methodof claim 7, further including aligning said processor carrier and saidconverter using at least two alignment pins.
 9. The method of claim 7,including providing substantially planar power and ground contacts oneach one of said processor carrier and said converter.
 10. The method ofclaim 9, including providing interdigitated power and ground contacts oneach one of said processor carrier and said converter.
 11. The method ofclaim 9, including arranging said substantially planar power and groundcontacts substantially parallel to the surface of said motherboard. 12.The method of claim 9, including causing the power signal pins to passthrough said substantially planar contacts.
 13. The method of claim 7,including securing said substrate to said processor carrier insubstantially the same direction that said processor carrier wasattached to the motherboard.
 14. The method of claim 7, includingsecurely clamping said converter onto said processor carrier.
 15. Themethod of claim 7, including causing said converter to lap saidprocessor carrier.
 16. The method of claim 7, including securing saidprocessor carrier to said motherboard before securing said converter tosaid carrier.
 17. A method comprising: plugging a DC-to-DC converter ontop of a processor carrier in turn secured to a motherboard; providingsubstantially planar power and ground contacts on said converter andsaid processor carrier; and engaging said contacts on said converterwith said contacts on said carrier such that said contacts aresubstantially parallel to said motherboard.
 18. The method of claim 17,including clamping said converter onto said processor carrier.
 19. Themethod of claim 17, including forming power and ground regions of thecontacts of said processor carrier and said converter andinterdigitating said power and ground regions.
 20. The method of claim17, including plugging said converter into said processor carrier. 21.The method of claim 20, including aligning said converter with saidprocessor carrier using alignment pins on one of said processor carrierand converter.
 22. The method of claim 17, including securing saidprocessor carrier to said motherboard in the same direction saidconverter is secured onto said processor carrier.
 23. A methodcomprising: attaching a processor carrier to a motherboard by movingsaid processor carrier onto said motherboard in a direction having acomponent transverse to the surface of said motherboard; securing aDC-to-DC converter to the processor carrier in a direction having acomponent transverse to the surface of said motherboard; and resilientlyclamping said converter and said carrier.
 24. The method of claim 23,further including aligning said processor carrier and said converterusing at least two alignment pins.
 25. The method of claim 23, includingproviding substantially planar power and ground contacts on each one ofsaid processor carrier and said converter.
 26. The method of claim 25,including arranging said substantially planar power and ground contactssubstantially parallel to the surface of said motherboard.
 27. Themethod of claim 23, including sandwiching a resilient interconnectbetween said carrier and said converter, and causing electricalcontinuity to be maintained through said interconnect.
 28. The method ofclaim 27, including forming conductive polymer contacts in saidinterconnect.
 29. The method of claim 23, wherein resiliently clampingsaid converter and said carrier includes clamping a housing having acompression spring formed therein onto said converter.
 30. The method ofclaim 28, including aligning contacts formed in said interconnect withcontacts on said converter and said carrier.
 31. The method of claim 30,including compressing said contacts between said carrier and saidconverter.
 32. The method of claim 28, including aligning saidinterconnect to said carrier.